Research fellow – Integrated circuit accelerators for in-memory computing
Learning from big data is the next big thing for a wide range of fields, including communications, industry, business, and healthcare. The von Neumann computer architecture is however not efficient for these tasks, due to the large energy and time needed for data movement between the memory and the CPU/GPU. In
the frame of an ERC project, we are developing in-memory computing accelerators for machine learning and data analytics, to process information within analogue memory circuits. Our technology enables one-shot learning with a 10,000x reduction of energy and time thanks to non-iterative computing in cross-point arrays of memories and memristors.
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